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Change the reset-value for RISCOF plugin

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This commit is contained in:
Konstantin Nazarov 2024-12-15 14:25:32 +00:00
parent a0a0ce30b4
commit 1b7ddce372
Signed by: knazarov
GPG key ID: 4CFE0A42FA409C22
1 changed files with 5 additions and 2 deletions
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7
test/rve/rve_isa.yaml
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@ -5,7 +5,10 @@ hart0:
User_Spec_Version: '2.3' User_Spec_Version: '2.3'
supported_xlen: [32] supported_xlen: [32]
misa: misa:
reset-val: 0x40001104 # reset-val encodes the CPU capabilities in a special register,
# as specified in https://five-embeddev.com/riscv-priv-isa-manual/Priv-v1.12/machine.html
# In this case, 32-bit with integer base ISA and multiplication/division
reset-val: 0x40001100
rv32: rv32:
accessible: true accessible: true
mxl: mxl:
@ -23,6 +26,6 @@ hart0:
warl: warl:
dependency_fields: [] dependency_fields: []
legal: legal:
- extensions[25:0] bitmask [0x0001104, 0x0000000] - extensions[25:0] bitmask [0x0001100, 0x0000000]
wr_illegal: wr_illegal:
- Unchanged - Unchanged