diff --git a/test/rve/rve_isa.yaml b/test/rve/rve_isa.yaml
index c195898..9f6e61e 100644
--- a/test/rve/rve_isa.yaml
+++ b/test/rve/rve_isa.yaml
@@ -5,7 +5,10 @@ hart0:
   User_Spec_Version: '2.3'
   supported_xlen: [32]
   misa:
-   reset-val: 0x40001104
+   # reset-val encodes the CPU capabilities in a special register,
+   # as specified in https://five-embeddev.com/riscv-priv-isa-manual/Priv-v1.12/machine.html
+   # In this case, 32-bit with integer base ISA and multiplication/division
+   reset-val: 0x40001100
    rv32:
      accessible: true
      mxl:
@@ -23,6 +26,6 @@ hart0:
            warl:
               dependency_fields: []
               legal:
-                - extensions[25:0] bitmask [0x0001104, 0x0000000]
+                - extensions[25:0] bitmask [0x0001100, 0x0000000]
               wr_illegal:
                 - Unchanged