398 lines
14 KiB
C++
398 lines
14 KiB
C++
#include "vm.hpp"
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#include <cstdint>
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#include <cstring>
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#include <fstream>
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#include <iostream>
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#include <stdexcept>
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#include <vector>
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inline int32_t sign_extend(int32_t value, int bits) {
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int32_t mask = 1 << (bits - 1);
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return (value ^ mask) - mask;
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}
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uint8_t UART::read_register(uint32_t address) {
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switch (address) {
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case UART_LSR:
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// Always ready to transmit
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return LSR_TRANSMITTER_EMPTY;
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default:
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return 0;
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}
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}
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void UART::write_register(uint32_t address, uint8_t value) {
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switch (address) {
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case UART_THR:
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std::cout.put(static_cast<char>(value));
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break;
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}
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}
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bool UART::is_transmitter_ready() {
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return read_register(UART_LSR) & LSR_TRANSMITTER_EMPTY;
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}
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VM::VM(const std::vector<uint8_t>& memory, const std::string& file_path)
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: memory_(memory), file_path(file_path) {}
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void VM::setreg(int regnum, uint32_t value) {
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if (regnum == 0) {
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return;
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}
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registers[regnum] = value;
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}
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std::vector<uint8_t> VM::read_memory(size_t start, size_t size) {
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if (start + size > memory_.size()) {
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return std::vector<uint8_t>(size, 0);
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}
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return std::vector<uint8_t>(memory_.begin() + start,
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memory_.begin() + start + size);
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}
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uint32_t VM::read_memory_word(size_t pos) {
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if (pos + 3 >= memory_.size()) {
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throw std::runtime_error("Memory access out of bounds");
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}
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return *(uint32_t*)&memory_[pos];
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}
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uint16_t VM::read_memory_half_word(size_t pos) {
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if (pos + 1 >= memory_.size()) {
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throw std::runtime_error("Memory access out of bounds");
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}
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return *(uint16_t*)&memory_[pos];
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}
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uint8_t VM::read_memory_byte(size_t pos) {
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if (pos >= memory_.size()) {
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throw std::runtime_error("Memory access out of bounds");
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}
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return memory_[pos];
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}
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void VM::write_memory_word(size_t pos, uint32_t value) {
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if (pos + 1 >= memory_.size()) {
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throw std::runtime_error("Memory access out of bounds");
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}
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*(uint32_t*)&memory_[pos] = value;
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}
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void VM::write_memory_half_word(size_t pos, uint16_t value) {
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if (pos + 3 >= memory_.size()) {
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throw std::runtime_error("Memory access out of bounds");
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}
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*(uint16_t*)&memory_[pos] = value;
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}
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void VM::write_memory_byte(size_t pos, uint8_t value) {
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if (is_mmap(pos, 1)) {
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if (pos >= UART_ADDR && pos < UART_ADDR + 8) {
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uart.write_register(pos - UART_ADDR, value);
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}
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return;
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}
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if (pos >= memory_.size()) {
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throw std::runtime_error("Memory access out of bounds");
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}
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memory_[pos] = value;
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}
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bool VM::is_mmap(size_t pos, size_t size) {
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if (pos + size < UART_ADDR) return false;
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if (pos >= UART_ADDR + 8) return false;
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return (pos < UART_ADDR + 8) && (pos + size >= UART_ADDR - 1);
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}
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uint32_t VM::read_register(size_t regnum) {
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if (regnum == 32) return pc;
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if (regnum >= NUM_REGISTERS) {
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throw std::runtime_error("Register out of range");
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}
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return registers[regnum];
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}
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const std::string& VM::get_file_path() { return file_path; }
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void VM::step() {
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uint32_t instr = *(uint32_t*)&memory_[pc];
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// std::cout << "pc: " << std::hex << pc << std::dec << "\n";
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// std::cout << "instr: " << std::hex << instr << "\n";
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pc += 4;
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// Decode instruction
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uint32_t opcode = instr & 0x7F;
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uint32_t rd = (instr >> 7) & 0x1F;
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uint32_t funct3 = (instr >> 12) & 0x7;
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uint32_t rs1 = (instr >> 15) & 0x1F;
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uint32_t rs2 = (instr >> 20) & 0x1F;
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uint32_t funct7 = (instr >> 25);
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int32_t imm;
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switch (opcode) {
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case 0x33: { // R-type
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if (funct7 == 0x00) {
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if (funct3 == 0x0) { // ADD
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setreg(rd, registers[rs1] + registers[rs2]);
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} else if (funct3 == 0x04) { // XOR
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setreg(rd, registers[rs1] ^ registers[rs2]);
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} else if (funct3 == 0x06) { // OR
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setreg(rd, registers[rs1] | registers[rs2]);
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} else if (funct3 == 0x07) { // AND
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setreg(rd, registers[rs1] & registers[rs2]);
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} else if (funct3 == 0x01) { // SLL
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setreg(rd, registers[rs1] << registers[rs2]);
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} else if (funct3 == 0x05) { // SRL
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uint32_t value = registers[rs1];
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uint32_t shift_amount = registers[rs2] & 0x1F;
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setreg(rd, value >> shift_amount);
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} else if (funct3 == 0x02) { // SLT
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setreg(rd, (static_cast<int32_t>(registers[rs1]) <
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static_cast<int32_t>(registers[rs2]))
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? 0
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: 1);
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} else if (funct3 == 0x03) { // SLTU
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setreg(rd, (registers[rs1] < registers[rs2]) ? 1 : 0);
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} else {
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throw std::runtime_error("Unknown R-type instruction");
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}
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} else if (funct7 == 0x20) {
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if (funct3 == 0x0) { // SUB
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setreg(rd, registers[rs1] - registers[rs2]);
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} else if (funct3 == 0x05) { // SRA
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// Only the lower 5 bits are used for shift
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int32_t value = static_cast<int32_t>(registers[rs1]);
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int32_t shift_amount = registers[rs2] & 0x1F;
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setreg(rd, value >> shift_amount);
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} else {
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throw std::runtime_error("Unknown R-type instruction");
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}
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} else if (funct7 == 0x01) {
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if (funct3 == 0x0) { // MUL
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int64_t result =
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static_cast<int64_t>(static_cast<int32_t>(registers[rs1])) *
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static_cast<int64_t>(static_cast<int32_t>(registers[rs2]));
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setreg(rd, static_cast<uint32_t>(result));
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} else if (funct3 == 0x1) { // MULH
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int64_t result =
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static_cast<int64_t>(static_cast<int32_t>(registers[rs1])) *
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static_cast<int64_t>(static_cast<int32_t>(registers[rs2]));
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setreg(rd, static_cast<uint32_t>(result >> 32));
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} else if (funct3 == 0x2) { // MULSU
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int64_t result =
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static_cast<int64_t>(static_cast<int32_t>(registers[rs1])) *
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static_cast<uint64_t>(registers[rs2]);
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setreg(rd, static_cast<uint32_t>(result >> 32));
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} else if (funct3 == 0x3) { // MULU
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uint64_t result = static_cast<uint64_t>(registers[rs1]) *
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static_cast<uint64_t>(registers[rs2]);
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setreg(rd, static_cast<uint32_t>(result >> 32)); // Upper 32 bits
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} else if (funct3 == 0x4) { // DIV
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int32_t dividend = static_cast<int32_t>(registers[rs1]);
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int32_t divisor = static_cast<int32_t>(registers[rs2]);
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if (divisor == 0) {
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setreg(rd, -1); // Division by zero result
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} else if (dividend == INT32_MIN && divisor == -1) {
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setreg(rd, dividend); // Overflow case
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} else {
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setreg(rd, dividend / divisor);
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}
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} else if (funct3 == 0x5) { // DIVU
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uint32_t dividend = registers[rs1];
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uint32_t divisor = registers[rs2];
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setreg(rd, (divisor == 0) ? UINT32_MAX : dividend / divisor);
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} else if (funct3 == 0x6) { // REM
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int32_t dividend = static_cast<int32_t>(registers[rs1]);
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int32_t divisor = static_cast<int32_t>(registers[rs2]);
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if (divisor == 0) {
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setreg(rd,
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dividend); // Remainder with zero divisor is the dividend
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} else if (dividend == INT32_MIN && divisor == -1) {
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setreg(rd, 0); // Overflow case
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} else {
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setreg(rd, dividend % divisor);
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}
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} else if (funct3 == 0x7) { // REMU
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uint32_t dividend = registers[rs1];
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uint32_t divisor = registers[rs2];
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setreg(rd, (divisor == 0) ? dividend : dividend % divisor);
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} else {
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throw std::runtime_error("Unknown R-type instruction");
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}
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} else {
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throw std::runtime_error("Unknown R-type instruction");
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}
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break;
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}
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case 0x13: { // I-type (ADDI and friends)
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imm = sign_extend(instr >> 20, 12); // Extract 12-bit immediate
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if (funct3 == 0x0) { // ADDI
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setreg(rd, registers[rs1] + imm);
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} else if (funct3 == 0x4) { // XORI
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setreg(rd, registers[rs1] ^ imm);
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} else if (funct3 == 0x6) { // ORI
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setreg(rd, registers[rs1] | imm);
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} else if (funct3 == 0x07) { // ANDI
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setreg(rd, registers[rs1] & imm);
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} else if (funct3 == 0x01) {
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if (((imm >> 5) & 0x7f) == 0x0) { // SLLI
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uint32_t value = registers[rs1];
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uint32_t shift_amount = imm & 0x1F;
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setreg(rd, value << shift_amount);
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} else {
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throw std::runtime_error("Unknown I-type instruction");
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}
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} else if (funct3 == 0x05) {
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if (((imm >> 5) & 0x7f) == 0x20) { // SRAI
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int32_t value = static_cast<int32_t>(imm & 0x1f);
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int32_t shift_amount = imm & 0x1F;
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setreg(rd, value >> shift_amount);
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} else if (((imm >> 5) & 0x7f) == 0x0) { // SRLI
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uint32_t value = registers[rs1];
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uint32_t shift_amount = imm & 0x1F;
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setreg(rd, value >> shift_amount);
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} else {
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throw std::runtime_error("Unknown I-type instruction");
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}
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} else {
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throw std::runtime_error("Unknown I-type instruction");
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}
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break;
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}
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case 0x63: { // B-type (branches)
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imm = ((int64_t)(int32_t)(instr & 0x80000000) >> 19) |
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((instr & 0x80) << 4) // imm[11]
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| ((instr >> 20) & 0x7e0) // imm[10:5]
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| ((instr >> 7) & 0x1e);
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if (funct3 == 0x0) { // BEQ
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if (registers[rs1] == registers[rs2]) {
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pc += imm - 4; // Offset PC (adjust for pre-increment)
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}
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} else if (funct3 == 0x1) { // BNE
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if (registers[rs1] != registers[rs2]) {
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pc += imm - 4; // Offset PC
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}
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} else if (funct3 == 0x4) { // BLT
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if (static_cast<int32_t>(registers[rs1]) <
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static_cast<int32_t>(registers[rs2])) {
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pc += imm - 4;
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}
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} else if (funct3 == 0x5) { // BGE
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if (static_cast<int32_t>(registers[rs1]) >=
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static_cast<int32_t>(registers[rs2])) {
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pc += imm - 4;
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}
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} else if (funct3 == 0x6) { // BLTU
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if (registers[rs1] < registers[rs2]) pc += imm - 4;
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} else if (funct3 == 0x7) { // BGEU
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if (registers[rs1] >= registers[rs2]) pc += imm - 4;
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} else {
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throw std::runtime_error("Unknown B-type instruction");
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}
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break;
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}
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case 0x03: { // I-type (loads)
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imm = sign_extend(instr >> 20, 12); // Extract 12-bit immediate
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if (funct3 == 0x00) { // LB
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uint32_t addr = registers[rs1] + imm;
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setreg(rd, read_memory_byte(addr));
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} else if (funct3 == 0x01) { // LH
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uint32_t addr = registers[rs1] + imm;
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setreg(rd, read_memory_half_word(addr));
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} else if (funct3 == 0x2) { // LW
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uint32_t addr = registers[rs1] + imm;
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setreg(rd, read_memory_word(addr));
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} else if (funct3 == 0x4) { // LBU
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uint32_t addr = registers[rs1] + imm;
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setreg(rd, read_memory_byte(addr));
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} else if (funct3 == 0x5) { // LHU
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uint32_t addr = registers[rs1] + imm;
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setreg(rd, read_memory_half_word(addr));
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} else {
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throw std::runtime_error("Unknown load instruction");
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}
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break;
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}
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case 0x23: { // S-type (SW)
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imm = ((instr >> 7) & 0x1F) | (((instr >> 25) & 0x7F) << 5);
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imm = sign_extend(imm, 12); // Sign-extend 12-bit immediate
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if (funct3 == 0x0) { // SB
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uint32_t addr = registers[rs1] + imm;
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write_memory_byte(addr, registers[rs2]);
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} else if (funct3 == 0x1) { // SH
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uint32_t addr = registers[rs1] + imm;
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if (addr + 2 > memory_.size()) {
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throw std::runtime_error("Memory access out of bounds");
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}
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std::memcpy(&memory_[addr], ®isters[rs2], sizeof(uint16_t));
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} else if (funct3 == 0x2) { // SW
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uint32_t addr = registers[rs1] + imm;
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if (addr + 4 > memory_.size()) {
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throw std::runtime_error("Memory access out of bounds");
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}
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std::memcpy(&memory_[addr], ®isters[rs2], sizeof(uint32_t));
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} else {
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throw std::runtime_error("Unknown store instruction");
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}
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break;
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}
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case 0x6F: { // JAL
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int32_t offset =
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((instr & 0x80000000) ? 0xFFF00000
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: 0) | // Sign-extension for imm[20]
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((instr >> 21) & 0x3FF) << 1 | // imm[10:1]
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((instr >> 20) & 0x1) << 11 | // imm[11]
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((instr & 0xFF000)); // imm[19:12]
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setreg(rd, pc); // Save return address
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pc += offset - 4;
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break;
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}
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case 0x67: { // JALR
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int32_t offset = (instr >> 20); // Sign-extended 12-bit immediate
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uint32_t target =
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(registers[rs1] + offset) & ~1; // Target address (LSB cleared)
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setreg(rd, pc); // Save return address
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pc = target;
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break;
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}
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case 0x37: { // LUI
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uint32_t imm = (instr >> 12) & 0xFFFFF; // Extract 20-bit immediate
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setreg(rd,
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imm << 12); // Shift the immediate to the upper 20 bits of the
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// register
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break;
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}
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case 0x17: { // AUIPC
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uint32_t imm = (instr >> 12) & 0xFFFFF; // Extract 20-bit immediate
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setreg(rd,
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pc - 4 + (imm << 12)); // Add the immediate (shifted left) to
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// the current PC
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break;
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}
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case 0x73: { // EBREAK
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pc -= 4;
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throw EbreakException();
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break;
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}
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default:
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throw std::runtime_error("Unknown opcode");
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}
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}
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void VM::eval() {
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while (true) {
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step();
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}
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}
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