Make riscof test suite actually compile the test binaries
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1b7ddce372
commit
d84c5022bd
2 changed files with 5 additions and 5 deletions
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@ -62,7 +62,7 @@ class rve(pluginTemplate):
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# Note the march is not hardwired here, because it will change for each
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# test. Similarly the output elf name and compile macros will be assigned later in the
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# runTests function
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self.compile_cmd = 'riscv{1}-unknown-elf-gcc -march={0} \
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self.compile_cmd = 'riscv{1}-none-elf-gcc -march={0} \
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-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g\
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-T '+self.pluginpath+'/env/link.ld\
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-I '+self.pluginpath+'/env/\
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@ -41,8 +41,8 @@ class sail_cSim(pluginTemplate):
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def initialise(self, suite, work_dir, archtest_env):
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self.suite = suite
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self.work_dir = work_dir
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self.objdump_cmd = 'riscv{1}-unknown-elf-objdump -D {0} > {2};'
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self.compile_cmd = 'riscv{1}-unknown-elf-gcc -march={0} \
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self.objdump_cmd = 'riscv{1}-none-elf-objdump -D {0} > {2};'
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self.compile_cmd = 'riscv{1}-none-elf-gcc -march={0} \
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-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles\
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-T '+self.pluginpath+'/env/link.ld\
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-I '+self.pluginpath+'/env/\
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@ -63,11 +63,11 @@ class sail_cSim(pluginTemplate):
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self.isa += 'f'
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if "D" in ispec["ISA"]:
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self.isa += 'd'
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objdump = "riscv{0}-unknown-elf-objdump".format(self.xlen)
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objdump = "riscv{0}-none-elf-objdump".format(self.xlen)
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if shutil.which(objdump) is None:
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logger.error(objdump+": executable not found. Please check environment setup.")
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raise SystemExit(1)
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compiler = "riscv{0}-unknown-elf-gcc".format(self.xlen)
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compiler = "riscv{0}-none-elf-gcc".format(self.xlen)
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if shutil.which(compiler) is None:
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logger.error(compiler+": executable not found. Please check environment setup.")
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raise SystemExit(1)
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