All opcodes except the syscalls
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1 changed files with 232 additions and 203 deletions
435
src/vm.cpp
435
src/vm.cpp
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@ -14,213 +14,242 @@ inline int32_t sign_extend(int32_t value, int bits) {
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}
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void eval(uint8_t* memory, size_t memory_size) {
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uint32_t registers[NUM_REGISTERS] = {0};
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uint32_t pc = 0;
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uint32_t registers[NUM_REGISTERS] = {0};
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uint32_t pc = 0;
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auto fetch_instruction = [&memory, &pc]() -> uint32_t {
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uint32_t instruction = 0;
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std::memcpy(&instruction, memory + pc, sizeof(uint32_t)); // Load 4 bytes (little-endian)
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return instruction;
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};
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auto fetch_instruction = [&memory, &pc]() -> uint32_t {
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uint32_t instruction = 0;
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std::memcpy(&instruction, memory + pc, sizeof(uint32_t)); // Load 4 bytes (little-endian)
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return instruction;
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};
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while (pc < memory_size) {
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uint32_t instr = fetch_instruction();
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if (instr == 0) break;
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// std::cout << "pc: " << pc << "\n";
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// std::cout << "instr: " << std::hex << instr << "\n";
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pc += 4;
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while (pc < memory_size) {
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uint32_t instr = fetch_instruction();
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if (instr == 0) break;
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// std::cout << "pc: " << pc << "\n";
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// std::cout << "instr: " << std::hex << instr << "\n";
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pc += 4;
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// Decode instruction
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uint32_t opcode = instr & 0x7F;
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uint32_t rd = (instr >> 7) & 0x1F;
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uint32_t funct3 = (instr >> 12) & 0x7;
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uint32_t rs1 = (instr >> 15) & 0x1F;
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uint32_t rs2 = (instr >> 20) & 0x1F;
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uint32_t funct7 = (instr >> 25);
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int32_t imm;
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// Decode instruction
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uint32_t opcode = instr & 0x7F;
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uint32_t rd = (instr >> 7) & 0x1F;
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uint32_t funct3 = (instr >> 12) & 0x7;
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uint32_t rs1 = (instr >> 15) & 0x1F;
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uint32_t rs2 = (instr >> 20) & 0x1F;
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uint32_t funct7 = (instr >> 25);
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int32_t imm;
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switch (opcode) {
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case 0x33: { // R-type
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if (funct7 == 0x00) {
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if (funct3 == 0x0) { // ADD
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registers[rd] = registers[rs1] + registers[rs2];
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} else if (funct3 == 0x04) { // XOR
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registers[rd] = registers[rs1] ^ registers[rs2];
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} else if (funct3 == 0x06) { // OR
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registers[rd] = registers[rs1] | registers[rs2];
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} else if (funct3 == 0x07) { // AND
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registers[rd] = registers[rs1] & registers[rs2];
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} else if (funct3 == 0x01) { // SLL
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registers[rd] = registers[rs1] << registers[rs2];
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} else if (funct3 == 0x05) { // SRL
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uint32_t value = registers[rs1];
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uint32_t shift_amount = registers[rs2] & 0x1F;
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registers[rd] = value << shift_amount;
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} else if (funct3 == 0x02) { // SLT
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registers[rd] = (static_cast<int32_t>(registers[rs1]) < static_cast<int32_t>(registers[rs2]))?0:1;
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} else if (funct3 == 0x03) { // SLTU
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registers[rd] = (registers[rs1] < registers[rs2]) ? 1 : 0;
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} else {
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throw std::runtime_error("Unknown R-type instruction");
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}
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} else if (funct7 == 0x20) {
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if (funct3 == 0x0) { // SUB
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registers[rd] = registers[rs1] - registers[rs2];
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} else if (funct3 == 0x05) { // SRA
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// Only the lower 5 bits are used for shift
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int32_t value = static_cast<int32_t>(registers[rs1]);
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int32_t shift_amount = registers[rs2] & 0x1F;
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registers[rd] = value >> shift_amount;
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} else {
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throw std::runtime_error("Unknown R-type instruction");
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}
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} else if (funct7 == 0x01) {
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if (funct3 == 0x0) { // MUL
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int64_t result = static_cast<int64_t>(static_cast<int32_t>(registers[rs1])) *
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static_cast<int64_t>(static_cast<int32_t>(registers[rs2]));
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registers[rd] = static_cast<uint32_t>(result);
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} else if (funct3 == 0x1) { // MULH
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int64_t result = static_cast<int64_t>(static_cast<int32_t>(registers[rs1])) *
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static_cast<int64_t>(static_cast<int32_t>(registers[rs2]));
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registers[rd] = static_cast<uint32_t>(result >> 32);
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} else if (funct3 == 0x2) { // MULSU
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int64_t result = static_cast<int64_t>(static_cast<int32_t>(registers[rs1])) *
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static_cast<uint64_t>(registers[rs2]);
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registers[rd] = static_cast<uint32_t>(result >> 32);
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} else if (funct3 == 0x3) { // MULU
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uint64_t result = static_cast<uint64_t>(registers[rs1]) *
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static_cast<uint64_t>(registers[rs2]);
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registers[rd] = static_cast<uint32_t>(result >> 32); // Upper 32 bits
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} else if (funct3 == 0x4) { // DIV
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int32_t dividend = static_cast<int32_t>(registers[rs1]);
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int32_t divisor = static_cast<int32_t>(registers[rs2]);
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if (divisor == 0) {
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registers[rd] = -1; // Division by zero result
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} else if (dividend == INT32_MIN && divisor == -1) {
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registers[rd] = dividend; // Overflow case
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} else {
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registers[rd] = dividend / divisor;
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}
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} else if (funct3 == 0x5) { // DIVU
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uint32_t dividend = registers[rs1];
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uint32_t divisor = registers[rs2];
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registers[rd] = (divisor == 0) ? UINT32_MAX : dividend / divisor;
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} else if (funct3 == 0x6) { // REM
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int32_t dividend = static_cast<int32_t>(registers[rs1]);
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int32_t divisor = static_cast<int32_t>(registers[rs2]);
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if (divisor == 0) {
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registers[rd] = dividend; // Remainder with zero divisor is the dividend
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} else if (dividend == INT32_MIN && divisor == -1) {
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registers[rd] = 0; // Overflow case
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} else {
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registers[rd] = dividend % divisor;
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}
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} else if (funct3 == 0x7) { // REMU
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uint32_t dividend = registers[rs1];
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uint32_t divisor = registers[rs2];
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registers[rd] = (divisor == 0) ? dividend : dividend % divisor;
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} else {
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throw std::runtime_error("Unknown R-type instruction");
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}
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} else {
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throw std::runtime_error("Unknown R-type instruction");
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}
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break;
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}
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case 0x13: { // I-type (ADDI)
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imm = sign_extend(instr >> 20, 12); // Extract 12-bit immediate
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if (funct3 == 0x0) { // ADDI
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registers[rd] = registers[rs1] + imm;
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} else {
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throw std::runtime_error("Unknown I-type instruction");
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}
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break;
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}
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case 0x63: { // B-type (branches)
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imm = ((instr >> 7) & 0x1E) | ((instr >> 20) & 0x7E0) |
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((instr >> 19) & 0x800) | ((instr >> 31) << 12);
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imm = sign_extend(imm, 13); // Sign-extend 13-bit immediate
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if (funct3 == 0x0) { // BEQ
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if (registers[rs1] == registers[rs2]) {
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pc += imm - 4; // Offset PC (adjust for pre-increment)
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}
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} else if (funct3 == 0x1) { // BNE
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if (registers[rs1] != registers[rs2]) {
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pc += imm - 4; // Offset PC
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}
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} else if (funct3 == 0x4) { // BLT
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if (static_cast<int32_t>(registers[rs1]) <
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static_cast<int32_t>(registers[rs2])) {
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pc += imm - 4;
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}
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} else if (funct3 == 0x5) { // BGE
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if (static_cast<int32_t>(registers[rs1]) >=
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static_cast<int32_t>(registers[rs2])) {
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pc += imm - 4;
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}
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} else if (funct3 == 0x6) { // BLTU
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if (registers[rs1] < registers[rs2]) pc += imm - 4;
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} else if (funct3 == 0x7) { // BGEU
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if (registers[rs1] >= registers[rs2]) pc += imm - 4;
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} else {
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throw std::runtime_error("Unknown B-type instruction");
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}
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break;
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}
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case 0x03: { // I-type (loads)
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imm = sign_extend(instr >> 20, 12); // Extract 12-bit immediate
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registers[rd] = 0;
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if (funct3 == 0x00) { // LB
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uint32_t addr = registers[rs1] + imm;
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if (addr + 1 > memory_size) {
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throw std::runtime_error("Memory access out of bounds");
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}
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std::memcpy(®isters[rd], memory + addr, sizeof(uint8_t));
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} else if (funct3 == 0x01) { // LH
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uint32_t addr = registers[rs1] + imm;
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if (addr + 2 > memory_size) {
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throw std::runtime_error("Memory access out of bounds");
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}
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std::memcpy(®isters[rd], memory + addr, sizeof(uint16_t));
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} else if (funct3 == 0x2) { // LW
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uint32_t addr = registers[rs1] + imm;
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if (addr + 4 > memory_size) {
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throw std::runtime_error("Memory access out of bounds");
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}
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std::memcpy(®isters[rd], memory + addr, sizeof(uint32_t));
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} else {
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throw std::runtime_error("Unknown load instruction");
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}
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break;
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}
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case 0x23: { // S-type (SW)
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imm = ((instr >> 7) & 0x1F) | ((instr >> 25) << 5);
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imm = sign_extend(imm, 12); // Sign-extend 12-bit immediate
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if (funct3 == 0x0) { // SB
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uint32_t addr = registers[rs1] + imm;
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if (addr + 1 > memory_size) {
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throw std::runtime_error("Memory access out of bounds");
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}
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std::memcpy(memory + addr, ®isters[rs2], sizeof(uint8_t));
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} else if (funct3 == 0x1) { // SH
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uint32_t addr = registers[rs1] + imm;
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if (addr + 2 > memory_size) {
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throw std::runtime_error("Memory access out of bounds");
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}
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std::memcpy(memory + addr, ®isters[rs2], sizeof(uint16_t));
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} else if (funct3 == 0x2) { // SW
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uint32_t addr = registers[rs1] + imm;
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if (addr + 4 > memory_size) {
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throw std::runtime_error("Memory access out of bounds");
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}
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std::memcpy(memory + addr, ®isters[rs2], sizeof(uint32_t));
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} else {
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throw std::runtime_error("Unknown store instruction");
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}
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break;
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}
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default:
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throw std::runtime_error("Unknown opcode");
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switch (opcode) {
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case 0x33: { // R-type
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if (funct7 == 0x00) {
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if (funct3 == 0x0) { // ADD
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registers[rd] = registers[rs1] + registers[rs2];
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} else if (funct3 == 0x04) { // XOR
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registers[rd] = registers[rs1] ^ registers[rs2];
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} else if (funct3 == 0x06) { // OR
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registers[rd] = registers[rs1] | registers[rs2];
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} else if (funct3 == 0x07) { // AND
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registers[rd] = registers[rs1] & registers[rs2];
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} else if (funct3 == 0x01) { // SLL
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registers[rd] = registers[rs1] << registers[rs2];
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} else if (funct3 == 0x05) { // SRL
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uint32_t value = registers[rs1];
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uint32_t shift_amount = registers[rs2] & 0x1F;
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registers[rd] = value << shift_amount;
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} else if (funct3 == 0x02) { // SLT
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registers[rd] = (static_cast<int32_t>(registers[rs1]) < static_cast<int32_t>(registers[rs2]))?0:1;
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} else if (funct3 == 0x03) { // SLTU
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registers[rd] = (registers[rs1] < registers[rs2]) ? 1 : 0;
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} else {
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throw std::runtime_error("Unknown R-type instruction");
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}
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} else if (funct7 == 0x20) {
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if (funct3 == 0x0) { // SUB
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registers[rd] = registers[rs1] - registers[rs2];
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} else if (funct3 == 0x05) { // SRA
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// Only the lower 5 bits are used for shift
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int32_t value = static_cast<int32_t>(registers[rs1]);
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int32_t shift_amount = registers[rs2] & 0x1F;
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registers[rd] = value >> shift_amount;
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} else {
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throw std::runtime_error("Unknown R-type instruction");
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}
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} else if (funct7 == 0x01) {
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if (funct3 == 0x0) { // MUL
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int64_t result = static_cast<int64_t>(static_cast<int32_t>(registers[rs1])) *
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static_cast<int64_t>(static_cast<int32_t>(registers[rs2]));
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registers[rd] = static_cast<uint32_t>(result);
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} else if (funct3 == 0x1) { // MULH
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int64_t result = static_cast<int64_t>(static_cast<int32_t>(registers[rs1])) *
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static_cast<int64_t>(static_cast<int32_t>(registers[rs2]));
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registers[rd] = static_cast<uint32_t>(result >> 32);
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} else if (funct3 == 0x2) { // MULSU
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int64_t result = static_cast<int64_t>(static_cast<int32_t>(registers[rs1])) *
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static_cast<uint64_t>(registers[rs2]);
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registers[rd] = static_cast<uint32_t>(result >> 32);
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} else if (funct3 == 0x3) { // MULU
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uint64_t result = static_cast<uint64_t>(registers[rs1]) *
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static_cast<uint64_t>(registers[rs2]);
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registers[rd] = static_cast<uint32_t>(result >> 32); // Upper 32 bits
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} else if (funct3 == 0x4) { // DIV
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int32_t dividend = static_cast<int32_t>(registers[rs1]);
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int32_t divisor = static_cast<int32_t>(registers[rs2]);
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if (divisor == 0) {
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registers[rd] = -1; // Division by zero result
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} else if (dividend == INT32_MIN && divisor == -1) {
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registers[rd] = dividend; // Overflow case
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} else {
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registers[rd] = dividend / divisor;
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}
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} else if (funct3 == 0x5) { // DIVU
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uint32_t dividend = registers[rs1];
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uint32_t divisor = registers[rs2];
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registers[rd] = (divisor == 0) ? UINT32_MAX : dividend / divisor;
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} else if (funct3 == 0x6) { // REM
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int32_t dividend = static_cast<int32_t>(registers[rs1]);
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int32_t divisor = static_cast<int32_t>(registers[rs2]);
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if (divisor == 0) {
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registers[rd] = dividend; // Remainder with zero divisor is the dividend
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} else if (dividend == INT32_MIN && divisor == -1) {
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registers[rd] = 0; // Overflow case
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} else {
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registers[rd] = dividend % divisor;
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}
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} else if (funct3 == 0x7) { // REMU
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uint32_t dividend = registers[rs1];
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uint32_t divisor = registers[rs2];
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registers[rd] = (divisor == 0) ? dividend : dividend % divisor;
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} else {
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throw std::runtime_error("Unknown R-type instruction");
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}
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} else {
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throw std::runtime_error("Unknown R-type instruction");
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}
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break;
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}
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case 0x13: { // I-type (ADDI)
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imm = sign_extend(instr >> 20, 12); // Extract 12-bit immediate
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if (funct3 == 0x0) { // ADDI
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registers[rd] = registers[rs1] + imm;
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} else {
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throw std::runtime_error("Unknown I-type instruction");
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}
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break;
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}
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case 0x63: { // B-type (branches)
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imm = ((instr >> 7) & 0x1E) | ((instr >> 20) & 0x7E0) |
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((instr >> 19) & 0x800) | ((instr >> 31) << 12);
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imm = sign_extend(imm, 13); // Sign-extend 13-bit immediate
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if (funct3 == 0x0) { // BEQ
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if (registers[rs1] == registers[rs2]) {
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pc += imm - 4; // Offset PC (adjust for pre-increment)
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}
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} else if (funct3 == 0x1) { // BNE
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if (registers[rs1] != registers[rs2]) {
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pc += imm - 4; // Offset PC
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}
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} else if (funct3 == 0x4) { // BLT
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if (static_cast<int32_t>(registers[rs1]) <
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static_cast<int32_t>(registers[rs2])) {
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pc += imm - 4;
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}
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} else if (funct3 == 0x5) { // BGE
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if (static_cast<int32_t>(registers[rs1]) >=
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static_cast<int32_t>(registers[rs2])) {
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pc += imm - 4;
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}
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} else if (funct3 == 0x6) { // BLTU
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if (registers[rs1] < registers[rs2]) pc += imm - 4;
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} else if (funct3 == 0x7) { // BGEU
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if (registers[rs1] >= registers[rs2]) pc += imm - 4;
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} else {
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throw std::runtime_error("Unknown B-type instruction");
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}
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break;
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}
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case 0x03: { // I-type (loads)
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imm = sign_extend(instr >> 20, 12); // Extract 12-bit immediate
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registers[rd] = 0;
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if (funct3 == 0x00) { // LB
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uint32_t addr = registers[rs1] + imm;
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if (addr + 1 > memory_size) {
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throw std::runtime_error("Memory access out of bounds");
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}
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std::memcpy(®isters[rd], memory + addr, sizeof(uint8_t));
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} else if (funct3 == 0x01) { // LH
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uint32_t addr = registers[rs1] + imm;
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if (addr + 2 > memory_size) {
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throw std::runtime_error("Memory access out of bounds");
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}
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std::memcpy(®isters[rd], memory + addr, sizeof(uint16_t));
|
||||
} else if (funct3 == 0x2) { // LW
|
||||
uint32_t addr = registers[rs1] + imm;
|
||||
if (addr + 4 > memory_size) {
|
||||
throw std::runtime_error("Memory access out of bounds");
|
||||
}
|
||||
std::memcpy(®isters[rd], memory + addr, sizeof(uint32_t));
|
||||
} else {
|
||||
throw std::runtime_error("Unknown load instruction");
|
||||
}
|
||||
break;
|
||||
}
|
||||
case 0x23: { // S-type (SW)
|
||||
imm = ((instr >> 7) & 0x1F) | ((instr >> 25) << 5);
|
||||
imm = sign_extend(imm, 12); // Sign-extend 12-bit immediate
|
||||
if (funct3 == 0x0) { // SB
|
||||
uint32_t addr = registers[rs1] + imm;
|
||||
if (addr + 1 > memory_size) {
|
||||
throw std::runtime_error("Memory access out of bounds");
|
||||
}
|
||||
std::memcpy(memory + addr, ®isters[rs2], sizeof(uint8_t));
|
||||
} else if (funct3 == 0x1) { // SH
|
||||
uint32_t addr = registers[rs1] + imm;
|
||||
if (addr + 2 > memory_size) {
|
||||
throw std::runtime_error("Memory access out of bounds");
|
||||
}
|
||||
std::memcpy(memory + addr, ®isters[rs2], sizeof(uint16_t));
|
||||
} else if (funct3 == 0x2) { // SW
|
||||
uint32_t addr = registers[rs1] + imm;
|
||||
if (addr + 4 > memory_size) {
|
||||
throw std::runtime_error("Memory access out of bounds");
|
||||
}
|
||||
std::memcpy(memory + addr, ®isters[rs2], sizeof(uint32_t));
|
||||
} else {
|
||||
throw std::runtime_error("Unknown store instruction");
|
||||
}
|
||||
break;
|
||||
}
|
||||
case 0x6F: { // JAL
|
||||
int32_t offset = ((instr & 0x80000000) ? 0xFFF00000 : 0) | // Sign-extension for imm[20]
|
||||
((instr >> 21) & 0x3FF) << 1 | // imm[10:1]
|
||||
((instr >> 20) & 0x1) << 11 | // imm[11]
|
||||
((instr & 0xFF000)); // imm[19:12]
|
||||
offset <<= 1; // Multiply by 2 (JAL offsets are word-aligned)
|
||||
|
||||
registers[rd] = pc; // Save return address
|
||||
pc += offset - 4;
|
||||
break;
|
||||
}
|
||||
case 0x67: { // JALR
|
||||
int32_t offset = (instr >> 20); // Sign-extended 12-bit immediate
|
||||
uint32_t target = (registers[rs1] + offset) & ~1; // Target address (LSB cleared)
|
||||
|
||||
registers[rd] = pc; // Save return address
|
||||
pc = target - 4;
|
||||
break;
|
||||
}
|
||||
case 0x37: { // LUI
|
||||
uint32_t imm = (instr >> 12) & 0xFFFFF; // Extract 20-bit immediate
|
||||
registers[rd] = imm << 12; // Shift the immediate to the upper 20 bits of the register
|
||||
break;
|
||||
}
|
||||
case 0x17: { // AUIPC
|
||||
uint32_t imm = (instr >> 12) & 0xFFFFF; // Extract 20-bit immediate
|
||||
registers[rd] = pc + (imm << 12); // Add the immediate (shifted left) to the current PC
|
||||
break;
|
||||
}
|
||||
default:
|
||||
throw std::runtime_error("Unknown opcode");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue